Mobile products (e.g., mobile phones, smart phones, tablet computers, etc.) are continually being designed to be more compact and portable. Therefore, it is extremely important to reduce the form factor, z-height and weight of the electronic devices that are included in mobile products.
One of the concerns that can arise as things are made smaller is signal integrity issues. As examples, channel impedance discontinuity and crosstalk are the common issues that are continually addressed during high-speed package and PCB design.
In some electronic devices, signal crosstalk is a common issue that occurs in conventional systems which include multiple high-speed parallel busses. Signal crosstalk issue may have negative design impacts by limiting the high-speed parallel bus design scaling (e.g., frequency, power, silicon real-estate, package layer-count and channel length).
Conventional solutions that seek to mitigate signal integrity issues typically require some form of design trade-off. One or more of these design trade-offs usually constrain enabling smaller form factor high-speed packages and PCBs as well as more compact high-speed packages and PCBs.
As a first example, high-speed packages and PCBs may increase the layer count and/or Z-height of the high-speed packages and PCBs. The number of signal routing layers and grounding layers may be increased to alleviate the signal integrity issues (e.g., due to breakout/congested routing areas or routing-over-void/split-plane areas).
As a second example, high-speed packages and PCBs may reduce routing density (i.e., increase in routing pitch). The layout of high-speed packages and PCBs may be optimized to reduce signal integrity issues by keeping interconnects with at least 2×-spacing away from one another to (i) reduce crosstalk; and (ii) have a transition to other routing layer to avoid routing over-void/split-plane areas.
As a third example, high-speed packages and PCBs may require an increase in power consumption. This increase in power consumption is typically combined with circuit patterns where active crosstalk cancellation and terminations are applied to mitigate crosstalk and reflection.
Therefore, a need exists for an interconnect structure that may address channel impedance discontinuity and crosstalk issues while minimizing any design trade-offs. Addressing channel impedance discontinuity and crosstalk issues while minimizing any design trade-offs may enable smaller form factor and more compact package & PCB designs. Smaller form factor and more compact package & PCB designs may be especially important in the mobile space of Wearables, Tablets, Smartphones and Ultrabooks (among other electronic devices).